Six Days Hands-on Workshop for final year E& C students on “VLSI Layout Design” Using Cadence Virtuoso Layout Editor.

A six days training program on “VLSI Layout Design” for the final year students was recently inaugurated at Smt.Kamala and Sri.Venkappa M..Agadi College of Engineering and Technology, Lakshmeshwar. Dr.S.V.Gorabal, Principal, inaugurated the training program on 1st, September, 2017. Speaking on the occasion, he said that there are many job opportunities for Electronics Engineers in the field of VLSI, provided that they are trained in the Verification and Testing aspects of VLSI circuits using Cadence Virtuoso tool. He commended the institute for providing training to the students in this core area and preparing them to face the challenge. Mr. Ravi Siddanath, Snr. IC Design Engineer, Broadcom, Bangalore, and Mr. Bhanuprakash, Design Engineer, Zia Semiconductor pvt. Ltd., Bangalore, who imparted the training to the students, said that India is currently having shortage of VLSI Professionals, and hence there is a bright future for VLS I trained students passing out of engineering colleges. Prof. Dr. N.Hayavadhana, the Academics Dean of SKSVMAC ET, Prof. Santosh S.Bujari, the HOD of E&CE of SKS VMACET who presided over the function, admired the students for opting for this training during their acade mics , and said that value additions mostly happen during academics. Prof.Krishna G.Deshpande, Workshop coordinator, Asst.Professor, Dept.of ECE, and other faculty members were present during the inaugural function.

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